This application relates to subject matter that may be similar to application Ser. No. 12/890,123 filed Sep. 24, 2010, the entirety of which is hereby incorporated by reference.
As known in the art, a plurality of production IC die are formed on a semiconductor wafer by performing semiconductor processing including lithography, etch, ion implant and thin film processes. Following formation of the IC die, the wafer is sawed for singulation of the die.
To assess electrical properties of elements (e.g., MOS transistors) constituting an IC die, a predetermined pattern of measuring elements or test elements (called test modules) are formed in the scribe line areas of the wafer to allow generation of in-line (i.e., production) test data. The test module is electrically tested by a test system including a probe card, prober system and measurement apparatus, and testing can be performed after deposition of an early metal interconnect level (e.g., first metal level) or after completion of wafer processing, for determining whether circuit elements such as MOS devices are suitably formed (e.g., have proper threshold voltage (Vt) and breakdown voltage) in the IC die on the wafer. Since the test module is formed using the same process as the process for forming the circuit elements formed on the IC die, and often having the same device layout, testing electrical properties of the devices in the test module can be identical to testing electrical properties of the circuit elements formed in the production IC die. Accordingly, the properties of the IC die can be generally be accurately deduced by testing the test modules.
One problem with scribe line measurements is that scribe lines are not within the actual production die boundary. Accordingly, scribe line measurements can be affected by surrounding devices and may provide measurements that indicate that the corresponding IC design requirements are met, while the actual IC die may not be in compliance. Moreover, scribe lines no longer exist after the wafers are singulated. Thus, if it is determined that there is a problem at the device level, there may be uncertainty as to where the problem originated. Moreover, it may be difficult to determine if the problem was due to a manufacturing error, was a transient problem that no longer exists, or is a problem in the design of the IC die.
Another method to assess electrical properties of elements constituting an IC die uses on-die parametric test modules that are placed on the production IC die. On-die parametric test modules can generally be placed anywhere on the die, since no specific pinout is needed. On-die parametric test modules can be tested at wafer final test, and at module or system test after singulation. Conventional on-die parametric test modules include arrays of MOS field effect transistors (FETs) having some particular device layout or a sampling of small area layout portions (e.g., digital logic gates) that match the device layout used for logic designs on the product IC die, which hold constant the various spacings (e.g., active area-to-active area spacing, and well-to-well spacing) in the device layout for the logic design.
Data processing from on-die parametric test modules comprising arrays of FETs can involve having their collective Ion measurements averaged, and recorded, along with threshold voltage (Vt) and effective drive current (Ieff) measurements, if applicable. This is done to account for spatial variations. Thus placement of a plurality of test modules across each IC die allows across the die parametric variation data to be extracted and analyzed.